library ieee;
use ieee.std_logic_1164.all;

-- Clock_out é de 100Hz se a entrada for 27MHz.

entity div_freq is
  port (clk, resetn : in     std_logic;
        divisao     : in     std_logic_vector (1 downto 0);
        clk_out     : buffer std_logic);
end div_freq;

architecture Behavior of div_freq is
  signal estado  : integer range 0 to 150;
  signal divisor : integer range 0 to 150;
begin

  process (divisao) is
  begin  -- process
    case divisao is
      when "00" =>
        divisor <= 150;
      when "01" =>
        divisor <= 70;
      when "10" =>
        divisor <= 30;
      when "11" =>
        divisor <= 15;
    end case;
  end process;

  process (clk, resetn) is
  begin  -- process
    if resetn = '0' then                -- asynchronous reset (active low)
      estado  <= 0;
      clk_out <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      if estado = divisor then
        estado  <= 0;
        clk_out <= not clk_out;
      else
        estado <= estado + 1;
      end if;
    end if;
  end process;
  
end Behavior;
